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Hi, I am Antonio Franques, and I am currently working at NVIDIA as a Senior Architect, focusing on GPU and SoC modelling.
Previously, I was part of the Platform Architecture group at Apple, working on performance modelling and analysis of on-chip interconnects in various SoCs.
I received my master’s and Ph.D. degrees in computer science from the University of Illinois at Urbana-Champaign (UIUC), under the supervision of Prof. Josep Torrellas, and as a member of the i-acoma group. My research focused on the application of novel interconnect technologies in large-scale multicore architectures. Specifically, I aimed to design scalable and efficient memory hierarchies to reduce the cost of data transfers, by using on-chip wireless communication.
While I was a graduate student at UIUC, I interned twice at AMD Research (Austin, TX, and Seattle, WA), developing and benchmarking driver and library software to evaluate the capabilities and performance of prototype interconnects for exascale computing.
Prior to joining UIUC, I obtained my bachelor’s degree in telecommunications engineering from the Technical University of Valencia (UPV), Spain, and completed one exchange semester at the Norwegian University of Science and Technology (NTNU), Norway.
During my undergraduate studies at UPV, I also performed two years of research in the area of computational mathematics under the supervision of Professors Juan Ramon Torregrosa and Alicia Cordero, as a member of the DAMRES group, developing numerical methods for nonlinear modeling.
Besides computer science related topics, my other personal interests and hobbies include running, hiking, rock climbing, traveling, and cooking.
You can find a copy of my full resume here, and a shorter version here. Also, you can email me at franque2@illinois.edu.
News
- Sep 2023: I have moved to NVIDIA to work as a Senior Architect, focusing on GPU and SoC modelling
- Aug 2021: I have joined Apple full-time, as an SoC Performance Architect
- Aug 2021: I have successfully defended my Ph.D. thesis, “On-Chip Wireless Manycore Architectures”
- Dec 2020: NeuMAC has been accepted to NSDI ‘21
- Nov 2020: Fuzzy-Token has been accepted to DATE ‘21
- Oct 2020: WiDir has been accepted to HPCA ‘21
- Aug 2020: Our poster Millimeter-Wave Wireless Network on Chip Using Deep Reinforcement Learning is among the winners of the Student Research Competition at SIGCOMM ‘20
- Feb 2020: Our manuscript Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication has been accepted to IEEE Transactions on Communications
- Oct 2019: I will be giving an invited talk at MICRO ‘19, titled Challenges and Opportunities of Wireless Network-on-Chip for Manycore Architectures
- Sep 2019: Our U.S. patent Communication Engine for Hybrid Interconnect Technologies has been issued on behalf of AMD
- Jul 2019: Serving on the NOCARC ‘19 Technical Program Committee. Submit your best work!
- Jan 2019: Heading off to AMD Research in Seattle for an extension of my previous internship
- Jan 2019: Our work on Opportunistic Beamforming in Wireless Network-on-Chip has been accepted to ISCAS ‘19
- Nov 2018: Replica has been accepted to ASPLOS ‘19
- Sep 2018: Heading off to AMD Research in Austin for an internship
- Jan 2018: Our work on Millimeter-Wave Propagation within a Computer Chip Package has been accepted to ISCAS ‘18
- Jul 2016: Our project receives an NSF XPS grant to advance scalability for on-chip wireless communications. NSF award site